Conventionally, there is known a sub-sampling PLL method in which a frequency divider is not used. In this method, a phase comparator sub-samples the output of a voltage-controlled oscillator (VCO) directly with a reference signal in order to achieve phase synchronization. Converting the phase difference between the reference signal and the VCO output directly into a voltage in this way leads to the advantage that high gain can be realized while restraining in-band PLL noise.
However, in the phase difference-current characteristics in the above method, positive and negative are reversed in the cycle of 2π. Accordingly, negative current is outputted when the phase difference shows that positive current should be outputted (when the phase is delayed, for example) or positive current is outputted when the phase difference shows that negative current should be outputted (when the phase is advanced, for example). In this case, a cycle slip phenomenon occurs and longer lockup time is required.